Power constraint communication-aware task scheduling in reconfigurable multiprocessors

Xiaoming Chen, Yan Liu, Renfa Li

COMPUTER MODELLING & NEW TECHNOLOGIES 2014 18(12B) 500-509

College of Computer Science and Electronic Engineering, Hunan University, Changsha 410082, Hunan, China
 

Heterogeneous multiprocessors with FPGA component have recently received a lot of attention due to its low cost and power consumption. However, most of existing works about task scheduling algorithm focus on minimization of system cost or power consumption. Actually, optimizing multiprocessor performance within a given power budget has recently received a lot of attention. Peak power consumption should be carefully controlled than directly improve computing performance. Furthermore, FPGA component in multiprocessors has essential parallelism ability to execute multiple tasks at same time using dynamic reconfigurable features. In this environment, tasks and communications should be carefully scheduled because their execution orders affect the performance of the whole chip. This paper presents an Integer Linear Programming (ILP) formulation that integrates the resource delay model and FPGA-component with pipelined scheduling and global power control. Moreover, to enhance the computation efficiency, a heuristic algorithm namely PCLS that integrates pipelined scheduling and global power control for heterogeneous multiprocessor architecture is proposed. Experiments show that our ILP method obtains the optimal results when task nodes are less than 35. Proposed PCLS heuristic algorithm achieves on average 10% higher makespan compare with DLS. For heavier synthetic task application, PCLS can provide only about 12% performance degradation under 70% power budgets based on different heterogeneous multiprocessor architectures.