Synthesis and simulation of digital pseudo-random impulse sequence generator based on PLIC FPGA Xilinx using CAD Vivado 2016.2 and development of acoustic noise generator scheme for the protection of information

A Zaurbek, N A Seilova, D Z Dzhuruntaev
COMPUTER MODELLING & NEW TECHNOLOGIES 2017 21(1) 39-46

Kazakh National Technical Research University named after K.I. Satpayev, Almaty, Kazakhstan

In this work with the help of CAD Vivado 2016.2 system and Verilog hardware description language there were synthesized, simulated and built temporary digital pseudo-random impulse sequence generator diagrams based on CAD of FPGA families of the Xilinx company and eight-rate shift LFSR register, which can be used in cryptography to create a stream encryption algorithms. On the basis of a digital pseudo-random impulse sequence generator and active low-pass filter of the second order of Sallen - Key there was constructed an electric diagram of the acoustic noise generator that provides protection against wiretapping by using embedded devices, telephone conversations, laser wiretapping system and unauthorized dictaphone recording of confidential voice information by creating a masking vibration noise.